The integration density of active components is a key factor in the development of new products. But technical boundaries and rising costs are limiting the structure size reduction. A three-dimensional stacking of chips, combined with wafer level processing, allows a functional extension and an increased complexity of electronic systems within minimum space.
The European joint project Master_3D aimed at the establishment of an integrated platform (tools, materials, processes) for the realization of three-dimensional innovative system in package (3D-SiP) solutions. Methods and technologies for highest contact density, thin silicon integration as well as new analytical and test procedures have been developed. This was done focusing on the goal to expand conventional assembly and connection technologies on wafer level into the third dimension, especially considering reliability, performance and process monitoring aspects. Within the project, IZM-ASSID achieved significant results in the development and performance increase of single processes that are technologically important for 3D integration. In cooperation with industrial partners, critical process steps were analyzed and evaluated considering real application scenarios and product requirements. Furthermore, in cooperation with tool suppliers, samples with dedicated 3D structures were produced and used for the evaluation and validation of newly developed process and inline monitoring tools.
In collaboration with NXP and Infineon, the achieved project results were applied in application-driven demonstrators which were realized with IZM-ASSID‘s technology line. In the NXP demonstrator, a security controller with an NFC interface (near field communication), an additional new security feature could be implemented by using 3D integration technologies. With this, the overall security level could be raised, too.
An extended understanding of the interaction of the individual processes and their effects on the electrical performance could be achieved by various, partly newly developed 3D test structures - a part of them interacting with the active components of the NXP CMOS wafer. The new 3D test structures in combination with the establishment of an enhanced test flow additionally allowed the collection of electrical data for every single 3D process module. With this, dedicated correlations of individual processes to yield detractors could be shown. Furthermore, a new concept for the integration of TSVs as a transistor gate in MOS transistors was initially successfully tested and assessed (vertical N- and P-MOS transistors).